1. Field of the Invention
This invention relates to electronic circuitry, and more particularly to circuits for multiplying two electrical signals.
2. Description of the Prior Art
Four-quadrant multiplier circuits ideally multiply together two voltage signals X and Y to produce an output which is proportional to the product of the two signal magnitudes, and has the correct algebraic sign. A popular circuit which employs an inverted form of a four-quadrant multiplier circuit is disclosed in the following articles by Barrie Gilbert: "A Precise Four-Quadrant Multiplier with Subnanosecond Response", IEEE Journal of Solid-State Circuits, vol. SC-3, pp. 365-373, December 1968; "A High Performance Monolithic Multiplier Using Active Feedback", IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 364-373, December 1974.
An equivalent schematic diagram of a circuit disclosed in the above references is shown in FIG. 1. Four current sources I1, I2, I3 and I4 are derived from the multiplied voltage signals X and Y in the form xI.sub.B, (1-x)I.sub.B, yI.sub.E and (1-y)I.sub.E, respectively, where x and y are respectively dimensionless indices of X and Y, in the range zero to unity, and I.sub.B and I.sub.E are fixed currents. A pair of npn transistors Q1 and Q2 conduct current through their collector-emitter circuits from a positive voltage bus V+ to I1 and I2, respectively. (While Q1 and Q2 are generally shown in the printed references as being diode connected, with their bases and collectors tied together, in practice they are normally formed with their bases connected to a separate bias point. The transistors operate in an equivalent fashion with either type of connection.)
The prior art multiplier circuit of FIG. 1 employs a pair of differential amplifiers to produce a multiplied output. The first amplifier comprises npn transistors Q3 and Q4, the emitters of which are connected together to supply current to I3, the bases of which are connected for biasing by the emitters of Q2 and Q1, respectively, and the collectors of which are connected to output lines 2 and 4, recpectively. The second differential amplifier is similar to the first, comprising npn transistors Q5 and Q6. The emitters of Q5 and Q6 are connected together to supply current to I4, their bases are connected for biasing by the emitters of Q1 and Q2, respectively, and their collectors are connected to output lines 2 and 4, respectively. As a result of this arrangement, output line 2 carries a current in the form (xy/2)I.sub.0 while output line 4 carries a current in the form of (1-xy/2)I.sub.0, I.sub.0 being a fixed output current.
A principal limitation of the FIG. 1 circuit is that, with a constant Y input voltage, the output is nonlinear with respect to changes in the X input voltage. This problem has been traced to mismatches which are present in conventional transistors, and occurs when the transistor saturation currents are not equal. In the 1974 Gilbert reference identified above it was shown that this X nonlinearity results from voltage offsets between the transistor pairs Q1,Q2 and Q3,Q4, and the transistor pairs Q1,Q2 and Q5,Q6. As little as 50 microvolts of offset voltage can produce a 0.1% nonlinearity. Thus, for a typical nonlinearity specifiction of 0.1%, very poor yields will be produced for integrated circuits using conventional processing techniques.
A circuit which addresses the offset voltage problem is disclosed in another article by Gilbert, "A Four-Quadrant Analog Divider/Multiplier with 0.01% Distortion", IEEE International Solid-State Circuits Conference, Feb. 25, 1983. In this circuit, illustrated in FIG. 2, small controlled voltage drops are introduced between the bases of Q1 and Q2 and the bases of the other transistors to compensate for the undesired offset voltages. The compensation voltages are developed across resistors R1, R2, R3 and R4 by means of trim currents I5, I6, I7 and I8, the trim currents being controlled by laser adjustment or other conventional means. While this circuit substantially resolves the offset voltage problem, the trim currents interfere with the normal operating currents in Q1 and Q2, causing large errors. These errors can be corrected by the addition of further compensation circuitry, but that adds to the complexity of the overall circuit.